Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time,