Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formu
