A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on