A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs
This paper analyzes the bit conversion errors in high speed SAR ADCs and proposes a design method to minimize their impact on the ADC performance. By removing the SR latch from the output stage of the differential comparator, while using only one comparator output to generate the differential signals for the internal capacitive DAC, sparkle-code errors are avoided, and conversion errors from a pre