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Blood treatment apparatus and method

A proposed blood treatment apparatus includes: a blood treatment unit (D), a pair of fluid pumps (PF1, PF2) and a pair of blood pumps (PB1, PB2). The blood treatment unit (D) is configured to receive untreated blood and fresh blood treatment fluid, and emit treated blood and used blood treatment fluid. The fluid pumps (PF1, PF2) are configured to pass blood treatment fluid through the blood treatm

On Intelligence

The present paper is little more than a modest “spin-off” from a larger historical project on intelligence in the early PRC. It raises and comments on some central aspects of PRC HUMINT penetration (and attempted penetration) of what the People’s Daily at the time called the “espionage apparatuses of the American and Chiang Kai-shek bandit gangs.”

Cooperation with Externalities and Uncertainty

We introduce a new class of cooperative games where the worth of a coalition depends on the behavior of other players and on the state of nature as well. We allow for coalitions to form both before and after the resolution of uncertainty, hence agreements must be stable against both types of deviations. The appropriate extension of the classical core concept, the Sustainable Core, is defined for t

Calibration of a mathematical model for anaerobic digestion with special emphasis on estimation of hydrolysis rate constants at 35, 55, and 60°C

Hydrolysis rate constants of sludge at 35°C, 55°C, and 60°C were found to be 0.32 d-1, 0.44 d-1, and 0.50 d-1, respectively in pilot-scale experiments with digestion of municipal sludge in semi-continuously operated reactors. The hydrolysis rate constants as well as estimated chemical oxygen demand (COD) fractions in the feed were implemented in a mathematical model for anaerobic digestion similar

Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias

In this paper we have proposed a test cost model for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike in the case of non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the most cost-efficient test flow for 3D TSV-SICs is yet undefined. Therefore, analysing the various alternatives of tes