Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
Semiconductor nanowires in wrapped, gate-all-around transistor geometry are highly favorable for future electronics. The advanced nanodevice processing results in strain due to the deposited dielectric and metal layers surrounding the nanowires, significantly affecting their performance. Therefore, non-destructive nanoscale characterization of complete devices is of utmost importance due to the sm