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We propose a technique for test scheduling and test bus infrastructure design. In our approach, we consider constraints on the power consumption and on the design for test resources, while minimizing the test application time and the test bus length. The technique has a low computational cost which is important when it is used repeatedly in the design space exploration process. For the final desig

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6th International Meeting on Electrochromism, August 29th - September 2nd, 2004, Brno University of Technology, Czech Republic.