A 53.3 Mb/s 4x4 16-QAM MIMO Decoder in 0.35um CMOS
An ASIC implementation of the K-best Schnorr-Euchner decoder is presented for a 4/spl times/4 16-QAM MIMO system. There are several low complexity and low power features incorporated in the proposed VLSI architecture. The chip is fabricated in a 0.35-/spl mu/m CMOS technology. The chip core area is 5.76 mm/sup 2/ with 91 K gates. Furthermore, the decoding throughput that the chip can support is up