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Ischemic Cell Death in the CNS - applications of a new in vitro model

Popular Abstract in Swedish När blodförsörjningen till hjärnan upphävs uppstår ett tillstånd av blodbrist, ischemi. När hela hjärnan drabbas, som vid ett hjärtstillestånd, kallas detta global ischemi medan fokal ischemi betecknar att blodflödet är upphävt i en del av hjärnan, som vid stroke. Hjärt- och kärlsjukdomar, till vilka stroke också räknas, utgör idag ett dominerande hälsovårdsproblem i väIschemic brain damage is a common cause of death and disability. A global ischemic insult is usually the result of a transient cardiac arrest while occlusion of cerebral blood vessels leads to focal ischemic lesions, commonly termed stroke. During the last decades our knowledge about the metabolic and cellular events leading to cell death following ischemia has expanded mainly due to experimental

Critique of the IPA vowel quadrangle, especially the use of vowel points in it

The globally widespread kind of description of vowels by points in the IPA quadrangle with the cardinal vowels as references is very often not trustworthy in its detailed specification. The reasonable interpretation of a dot registration is namely that the vowel quality is very narrowly pinpointed. However, most phoneticians do not have the capacity to judge vowels in this detailed way. Consequent

The development of fair trade labels – A market solution to a societal concern?

Consumers are increasingly taking an interest in how their food is produced. Concerns are being voiced that practices that are environmentally harmful, involve maltreatment of animals or exploit poor and vulnerable farmers, should be avoided. The term societal concern has been coined for concerns that are derived from broadly shared values within a society, often entailing an ethical dimension. Th

A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS

The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read f