A 65-nm CMOS Low-Power Front-End for 3rd Generation DNA Sequencing
A continuous-time, 65-nm CMOS, front-end for processing DNA sequencing measurements from biological nanopore sensors is presented. The measured design has an input referred noise floor of 8.5\;{\text{fA}}/\sqrt {{\text{Hz}}} for 100 pA DC current while consuming 10X less power. The chip also consists of an integrated ADC.