Design and measurement of a CT delta-sigma ADC with switched-capacitor switched-resistor feedback
The performance of traditional continuous-time (CT) delta-sigma analog-to-digital converters (ADCs) is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback digital-to-analog converters (DACs). To mitigate that effect, we propose a modified switched-capacitor (SC) feedback DAC technique, with a variable switched series resistor (SR). The arc