Scheduling Tests for 3D Stacked Chips under Power Constraints
This paper addresses Test Application Time (TAT) reduction under power constraints for core- based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the op
