Pushing the limits of standard CMOS
An improved clocking scheme and sharper circuit design and logic selection, which have yielded a five-to-tenfold increased in the speed of standard CMOS ICs, are discussed. The clocking strategy relies on a true single-phase clock, device sizes are varied to optimize their speed, and a precharged logic style reduces capacitive loads. The tradeoff is roughly a doubling of circuit area. The high-spe