Design and implementation of testable fault-tolerant RISC-V system
This thesis aims to investigate and implement a fault-tolerant energy-efficient RISC-V based system on chip (SoC). Key features of the SoC is the testabil- ity and reliability of the low power on-chip embedded memories. A built-in self- test (BIST) for the on-chip memories has been designed and implemented to run on-demand diagnostic tests to detect manufacturing errors in the memories. It incor
