Scheduling Tests for Stacked 3D Chips under Power Constraints
This paper addresses test application time (TAT) reduction for core-based stacked 3D chips. In contrast to the traditional method of testing non-stacked chips where the same test schedule is applied both at wafer test and at final test, stacked 3D chips need a pre-bond test schedule for each individual chip and a different post-bond test schedule where all chips are jointly tested. We consider a s