DLL Based Reference Multiplier for the use in a PLL for WLAN applications
This master’s thesis project report deals with the design of multiplier for the reference signal to the Phase Locked Loop (PLL) used in WLAN application. The reference multiplier designed is based on a newly proposed architecture of dual loop feedback Delay Locked Loop (DLL) in which multiplication is performed within the loops. To lock the DLL, input signal is required to be delayed only for threKamal Kumar Gupta DLL Based Reference Multiplier for the use in a PLL for WLAN applications In modern wireless communication system, a frequency synthesizer/multiplier is one of the main building blocks of the system. For on-chip application, a frequency synthesizer is used as local oscillator (LO) to generate precise frequency from a single base frequency source, usually a crystal oscillator. Th