A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
The increasing test application times required for testing system-on-chips (SOCs) is a problem that leads to higher costs. For modular core based SOCs it is possibly to employ a concurrent test scheme in order to lower the test application times. To allow each core to be tested as a separate unit, a wrapper is inserted for each core, the scan chains at each core are configured into a fixed number
