Search results

Filter

Filetype

Your search for "*" yielded 534488 hits

System-on-Chip Test Bus Design and Test Scheduling

We propose a technique for test scheduling and test bus infrastructure design. In our approach, we consider constraints on the power consumption and on the design for test resources, while minimizing the test application time and the test bus length. The technique has a low computational cost which is important when it is used repeatedly in the design space exploration process. For the final desig